1. Field of the Invention
The present invention relates to a semiconductor device formed using a single crystal silicon substrate and, more particularly, to a configuration of an insulated gate field effect transistor (referred to as "MOSFET" or "IGFET").
The present invention is a technique which is effective for the fabrication of a fine device having a channel length and a channel width equal to or less than 1 .mu.m (typically in the range from 30 to 500 nm).
The present invention can be applied to various semiconductor integrated circuits such as ICs, VLSIs and ULSIs which are formed by integrating MOSFETs.
2. Description of the Related Art
Recently, integrated circuits such as VLSIs are becoming increasingly finer, which has resulted in a need for processing dimensions in a deep submicron domain wherein the channel length (L) of a MOSFET is 0.2 .mu.m or less, more preferably, 0.1 .mu.m or less.
Similarly, processing dimensions as fine as 0.2 .mu.m or less are also required for the gate width (W), and a device size satisfying a relationship L:W=1:1 has been proposed.
However, a phenomenon referred to as "short channel effect" is known as a factor which hinders semiconductor devices from being made finer. The short channel effect represents various problems such as a decrease in a withstand voltage between a source and a drain and a decrease in a threshold voltage which occur as a result of a decrease in a channel length. The short channel effect is detailed in "Mitsumasa Koyanagi et al., "Submicron Device I, pp. 88-138, Maruzen K. K., 1987.
According to this article, one of the most commonly known causes of a decrease in a withstand voltage is punch-through which is a phenomenon wherein, as a result of a decrease in a channel length, electric potential at a depletion layer toward the drain (referred to as "drain-side depletion layer) affects a region toward the source to decrease diffusion potential near the source (drain-induced barrier reduction), thereby making it difficult to control carriers using a gate voltage.
FIGS. 3A and 3B schematically show how this occurs. In FIGS. 3A and 3B, 301 represents a single crystal silicon substrate; 302 represents a source region; 303 represents a channel formation region; 304 represents a drain region; 305 represents a field oxide (device separation insulator); 306 represents a gate insulator; and 307 represents a gate electrode. The dotted line indicated by 30 represents a depletion layer formed during the operation.
Normally, a depletion layer having a uniform depth is formed under a channel which is formed directly under the gate electrode 307. However, when the channel length (L) is extremely short, a depletion layer that extends from the side of the drain drain-side depletion layer) comes into contact with a depletion layer toward the source as indicated by the arrow in FIG. 3A.
As a result, a potential barrier in the vicinity of the source is decreased by the drain voltage to cause an unintended flow of a current even when no gate voltage is applied. This is the so-called "punch-through" which can reduce the withstand voltage between the source and drain.
There is a phenomenon called "impact ionization of implanted carriers" which is another cause of a decrease in the withstand voltage between the source and drain. A description will be made on the same with reference to an n-channel MOSFET as an example.
When electrons (majority carriers) are pulled by a strong electric field to reach a high energy state in the vicinity of the drain, they collide with a silicon lattice to generate a great amount of electron-hole pairs. The holes thus generated (minority carriers) are pushed back by the electric field of the drain and flow into the source terminal or substrate terminal through a depletion layer under the channel or the substrate. Those holes cause a breakdown phenomenon induced by the implantation of the carriers.
There are two mechanisms for this. Specifically, one of the mechanisms is that a hole current flowing into the substrate terminal causes conduction through a parasitic bipolar transistor which is formed by the source, substrate and drain serving as an emitter, base and collector, respectively.
The other mechanism is that the holes which have flowed into the depletion layer of the substrate in the vicinity of the source reduce the diffusion potential near the source to reduce the potential barrier.
While various measures have been taken against the short channel effect as described above, the most common measure is channel doping. Channel doping is a technique to shallowly dope the entire channel formation region with a very small amount of an impurity element such as P (phosphorus) or B (boron) to suppress the short channel effect (see Japanese unexamined patent publications (KOKAI) No. H4-206971 and No. H4-286339).
However, channel doping has a problem in that it places a significant limitation on field effect mobility of a MOSFET (hereinafter simply referred to as "mobility"). Specifically, an intentionally added impurity element interferes with the movement of the carries to reduce the mobility of the same.
For example, there is a report indicating that mobility achievable in conventional standard MOSFETs is only 300 cm.sup.2 /Vs for n-channel MOSFETs and 70 cm.sup.2 /Vs for p-channel MOSFETs (See D. T. Grider et. al., "Symposium on Technology Digest of Technical Papers", pp 47, 1997).
The present invention has been conceived taking the above-described problems into consideration, and it is an object of the invention to provide a semiconductor device having a novel structure with which high reliability and high field effect mobility can be achieved simultaneously.